1. Field of the Invention
The present invention relates to a semiconductor device in which semiconductor epitaxial layers are embedded in the source/drain regions in order to apply a stress to the channel region, and silicide layers are formed on the epitaxial layers, and a method of fabricating the semiconductor device.
2. Description of the Related Art
From the 90-nm generation of semiconductor process nodes, techniques that improve the transistor performance by applying a stress to the channel region have been used. Examples are a technique that improves the performance of an nMOSFET by using a stress liner, a DSL (Dual Stress Liner) technique using optimum stress liners for both n and p, and an eSiGe (embedded SiGe) technique by which SiGe is embedded in the source/drain regions.
The eSiGe technique can apply a compression stress on an Si channel by embedding SiGe layers in the source/drain regions sandwiching the Si channel, thereby increasing the mobility. In addition, the resistance of the source/drain can be decreased by forming silicide layers on the SiGe layers.
Unfortunately, the eSiGe technique of this kind has the following problem. That is, a silicide to be formed on the SiGe layer is formed by siliciding the SiGe layer. In this silicidation, a silicide abnormally grows toward substrate Si having a silicidation reactivity higher than that of SiGe. This abnormal growth of the silicide to substrate Si increases the junction leakage.